The name was inspired by the fact that I have half a dozen abandoned DACs in my projects folder from the last 3 years, and this was just yet another DAC.
I've been messing with DAC designs on and off for the last few years, and finally got serious about it a few weeks ago. Here's what I've got so far. This is designed to be an ultra high end DAC with no corners cut anywhere (within mathematical reason). The bill of materials comes in well over $1000 and I'm trying to convince myself to actually build this thing.
This is a first draft of the board set: power supply, DAC (4-layer), and I-V stage. And of course four transformers to the left. Not pictured is a front panel with an LCD display.
DAC's: Quad of PCM1704U-K (Using a quad since it allows balanced output with a minimalist I-V stage)
Overall concept: NOS at 96khz, optional 2x oversampling at 48khz. User selectable filterless or single-pole 22khz roll off.
Architecture: FPGA FIFO reclocking for bit-perfect playback.
Clocks: Crystek CVHD-957 at 22.5792MHz and 24.576MHz
Clock Distribution: 50 ohm parallel terminated impedance matched transmission line with ultra low jitter 10x clock breakout Texas Instruments CDCLVC1310
Overall clock performance: Depending on how you define jitter and run the math, 100-300fs at the actual DAC chips
Power: 12 isolated power windings, 4 toroidal transformers, 18 application-specific pre-regulators, and 29 local LDO or shunt regulators
Chassis: Custom CNC milled aluminum, maybe even unibody if I can find a cheap billet of aluminum laying around
Front panel: LCD display with button interface to select output filter, oversampling options, bit-perfect testing, and whatever other options I come up with along the way
The main logic is run through a Spartan 6 FPGA. This talks to a CS8414 receiver chip (a great chip since it allows easy bit-perfect access to the incoming stream) and gets the input data and establishes the sampling rate. The FPGA then fabricates its own clock at 256fs by controlling a 16-bit DAC (AD5061BRJZ-2REEL7) connected to a VCXO. The FPGA runs a control loop that maintains a constant FIFO buffer length. I'm planning to have bounds, and it just adjusts the clock every few tens of seconds to bounce to the other bound, and repeat. While this may sound like a bad idea, changing the clock by a few hertz here and there adds single digit femtosecond jitter events, so it doesn't matter at all!
Clocks and Distribution
One of the most important parts of a DAC is the clock. In this case, I'm using VCXO crystals from Crystek (CVHD-957) that have phenomenal phase noise performance (by far the best in the industry for VCXO). They are immediately fed into a TI CDCLVC1310 clock breakout chip, which adds only 25fs of jitter and 30ps of skew. Perfect for this application! All outputs are fed through 50 ohm traces to parallel vcc/2 termination at destination. All traces are length-matched to reduce any further skew. 4 clocks are sent to PCM1704's, 1 to the FPGA, and 4 clocks are sent to 74-series flip-flop reclockers (arguably redundant for PCM1704, but whatever let's just do it... I'd rather the FPGA not directly touch the DAC chips at all).
The entire clock system is powered by five individual TPS7A4700 4.17uV ultra low noise LDO regulators, and pre-regulated by five LT1965 low-noise LDO regulators.
These chips require four power supplies each, which is a bit annoying. To keep everything symmetric, I'm using TL431 shunt regulators (16 of them for the four chips). Each regulator is fed by a BJT constant current source biased by another TL431. Pictured is the quad of regulators for one chip:
I got a bit creative with the pre-regulator for this one. since it is a pure constant current draw for the entire rail, we don't actually need low impedance but instead extremely low noise is the only goal. Therefore, the pre-regulator actually has no feedback and instead is just a FET follower with constant gate voltage. The gate voltage is set by a zener resistor powered by a CRCRCRC filter. This has extremely good PSRR where it counts (better than any discrete LDO), and should be only a few uV of noise. This supply is powered by its own physical transformer so as to avoid loading from other secondaries causing low frequency noise that this pre-regulator might struggle with. Here is the pre-reg and its output PSRR:
The IV stage uses a single BJT emitter input as the active signal path with a cascoded current mirror on both sides of the BJT. The output then goes to a 0.1% resistor and an optional relay-activated 22khz single-pole filter. The output is capacitor decoupled (I believe in capacitors because I am an engineer - let's not make this thread about whether or not the final output stage deserves to be DC coupled). This I-V stage is powered by basically the exact same supply used to pre-regulate the PCM1704 chips. Again, this is a pure constant current draw, and again it will have its own transformer to avoid cross-coupling of low frequency noise.
Well, I have to convince myself to dump about $1200 into this project. I'll probably start out building it single ended to save money and test everything (or is this a bad idea because I need PCM1704's from the same batch?).
The board files are not quite ready to be released, but I will (probably) open source this project at some point.
Any ideas? Did I do something stupid? Did I do something you disagree with? Do you have any suggestions/questions? Do you want to say something? Can you convince me to build it?