And even better source for tech savvy.
Essentially this is ASRC stage that can be disabled, or at least this is my reading of it.
The Sabre DAC uses the Phase Lock Loop to lock unto an incoming signal. For I2S, it locks to the bitclock.
DPLL Values: The DPLL bandwidth can be set to the following values: “lowest”, “low”, “medium-low”, “medium”, “medium-high”, “high”, “highest” and “best”; there is also a 128x setting which apparently multiplies the bandwidth values x128.
The DPLL has adjustable bandwidth. Setting the bandwidth to its lowest value results in maximum jitter reduction. However if the bandwidth is “too low”, the DPLL will loose lock and you will hear dropouts. Thus the usable lowest bandwidth setting is one where no dropouts occur. I have done extensive testing with the different settings of the DPLL. Here is a summary on how it behaves:
- “Best” setting works all the time for everything
- “Lowest” works for SPDIF input but never works for I2S input except for a few exceptionally modded I2S devices. Thus the lowest setting depends on the input format
- The lowest setting depends on the incoming sample rate. The higher the sample rate, the higher the lowest setting
- The lowest setting will not work when the DAC is cold (right after power-0n). The “warm up” period is 15-30 minutes
I wrote 3 posts on the DPLL describing its behavior further:
Relation of dpll bandwidth setting in SPDIF and I2S
Fidelix indicate that the DPLL bandwidth setting for I2S is 64x smaller than in SPDIF. This was confirmed by the manufacturer. So:
- “Lowest” is 64X smaller in I2S than “Lowest” in SPDIF (1/64 the same setting in SPDIF)
- “Low” is 32X smaller in I2S than “Lowest” in SPDIF
- “Mid-Low” is 16X smaller in I2S than “Lowest” in SPDIF
- “Mid” is 8X smaller in I2S than “Lowest” in SPDIF
- “Mid-High” is 4X smaller in I2S than “Lowest” in SPDIF
- “High” is 2X smaller in I2S than “Lowest” in SPDIF
- “Highest” is the same as “Lowest” in SPDIF