DIY Discrete R-2R Ladder DAC: Serial Data Demultiplexing

You seem to know what you're doing so I can probably be a bit vague. the pcm stream is signed, which means that the most significant bit is used for telling wether it is positive or negative number. You can design a circuit that looks at that first bit. If the first bit is 0, send all data along circuit A into the section that handles unsigned data without a hitch. If the MSB is 1, however, send the data to a converter that will change from signed to unsigned.

My worry here is that changing from signed to unsigned might just do what a full wave rectifier does and simply make your negative number positive. Instead, I think the next option is to figure out the lowest number possible and the absolute value of that number to your output. That way instead of going from -255 to +255, you are going from 0 to 510. I think using R-2R method this is the only way unless your register itself can handle signed integers.

I know I didnt really provide a solution but maybe I sparked an idea or something.

Are you sure you've seen them make a discrete DAC that supports the PCM and I2S standard? Or have they just built a DAC that only works with unsigned numbers? I can see how an R-2R dac would work in that respect, but otherwise I have no idea.

You could use the MSB as a mux switch but have your positive numbers only get sent to the first r/2r dac and get negative data sent to the other dac? i'm picturing a dac that is twice as "wide" as it needs to be and wiring it up so that negative numbers from -255 to 0 go to the "right" dac, and only registers 0-255, and postive numbers get sent also to the "right" dac and register 256-510?

I would think you could build a finite state machine in TTL logic running off the bit and word clocks to do this.

 

It'd be easier implement it in a CPLD but I doubt you have the resources to accomplish this. You'd need to learn VHDL or some kind of hardware programming language and you'd need a CPLD programmer.

 

In either case you'd have a 24-bit serial-in-to-parallel-out shift register (3 * 8-bit TTL registers in series) and a 24-bit parallel-in-to-serial-out shift register. You'd clock the data into the first register bit-by-bit until you'd accumulated 24 bits, then parallel shift them into the output register (triggered by the word clock), rearranging the bit order and sorting out the sign bit. This would be hardwired. You might need an intermediate holding register or 2 (pipelining) causing the output to lag the input by 2 or even 3 word clocks. The bit and word clocks would control the serial shifting and parallel shifting respectively, synch would be automatic.

 

It's a long time since I did this kind of thing in discrete logic, so I don't remember exactly what kinds of registers are available in TTL, but as a general rule, there are enough different flavours to implement anything you can imagine.

 

Is that enough for you to figure out what I mean, or do I need to be more explicit?

 

w

Edited by wakibaki - 2/12/12 at 7:15pm

Yes, thinking about it, that's correct.

 

If these were 8-bit numbers, you'd want

 

1000 0000 (-128) to become 0 (0000 0000)

1111 1111 (-1) to become 127 (0111 1111)

0000 0000 (0) to become 128 (1000 0000)

0111 1111 (127) to become 255 (1111 1111)

 

I can't see how you've built your DAC though, so I don't know how feasable it is to invert that bit. If you need to invert the bit in the datastream, the back-to-back serial/parallel parallel/serial shift registers with the MSB inverted will accomplish it without synch issues or a heroic programming effort.

 

w

Edited by wakibaki - 2/12/12 at 8:17pm

Keeping the 8bit number example from wakibaki, you can add 128 to every byte (number).

You will definetly get a over flow  (aka carry bit) on negative number, but just discard it!

 

1000 0000 (-128) + 1000 0000 (128) become 0 (1 0000 0000)

1111 1111 (-1) + 1000 0000 (128) become 127 (1 0111 1111)

0000 0000 (0) + 1000 0000 (128)to become 128 (1000 0000)

0111 1111 (127) + 1000 0000 (128) to become 255 (1111 1111)

 

/bonker

^^ adding 128 and discarding the carry out bit is the same as inverting the MSB, which seems simpler to me.

 

I have been thinking about this project a little as it is pretty interesting, but I have one question. It seems to me that if you want a 24 bit DAC using this method you will need extremely accurate resistors. For example your standard 1% resistors are only going to get you about 8 bits right? Are you using laser trimmed resistors like zfoils? Or some other method like less accurate resistors but many DACs in parallel?

even with standard zfoils it would be hard, you could get texas components to make you up some trimmed and matched z or sfoil resistor networks, but $$$.

 

seems this would only be a project for fun, to get an actual usefully accurate dac you are up for a huge project and a lot of expense to only end up with a device that replicates yesterdays tech, which is available NOS anyway. theres a reason large companies do this and flagships tend to stay around a while, its one of the slower moving product lines in any company's catalogue because its a huge undertaking. Z or S foils would be the way to go though, due to their almost complete immunity to changing value with tempco, frequency etc. even with matched resistors you would probably need to pot the whole thing when youre done to help keep temperature stable.

 

all the same, kudos for the effort and i'll be watching with interest