Originally Posted by cobaltmute
How thick are you talking about? The thin traces are 15mil and the thick ones are 50mil.
I like to get signal traces up to 40-50 mil if I can manage it on a given layout. That works well with standard 0.1" pin spacing components. Down around your SO-8 chip you'll have to neck things down a bit.
As for the power traces, I design those heuristically. There is no one rule, and the rules I use often conflict so I have to balance them against each other. The ones that come immediately to mind are:
- Prefer running major power and ground signals as planes rather than traces
- When using traces instead, pick a size as large as possible on your board. Consider it the "bus width" in that particular design. There are a few such in the YJPS, for instance, over 100 mil. 150 maybe? That's probably too much for a board this compact. The point is, pick a size and stick to it. Use it only for those connections that can't be readily made with a plane, such as connecting two planes together.
- AC side should be kept from DC side by at least 8mm. Use your CAD package's DRC rules to enforce this.
- Keep space between unregulated and regulated DC sides.
- Keep space around pads. Your board maker might be capable of 6/6 spacing, but that doesn't mean you need to push it that hard. I like to use more like 12-20 mil.
- Use relatively thin trace widths for pours; 8-12 mll. This heuristic and the previous one combine to ensure that fenestrations do indeed improve solderability. Your current fenestrations are scarcely better than doing without because the four connections are so thick and the spacing so tight. That turns the plane into a big heat sink, increasing joint creation time and increasing the risk of cold joints and damaged components.
what traces on what layers?
The first choice to make is whether you put the planes on the outer layers and the signals inside, or vice versa. The first choice is better for RF immunity and low-noise performance, while the second is better for DIY hackability. Another thing to consider is that the outer layers will have thicker copper. This tends to argue for putting the planes inside since they make up for thickness with area; let the outer layers get the benefit of thicker copper on the relatively thin traces.
You probably want two layers dedicated to signals, one the primary signal layer, the other the "I need to jump this signal over that other one" layer. You use these like in 2-layer design.
The other two layers are for planes. In old-school digital design, it was easy: one is +5V and the other GND. For this design, maybe they are unregulated ground and regulator ground instead. There should be no need for a +V plane, since the connection from the pass transistor emitter to the VOUT connector should be very short.
Speaking of, that do-si-do you've got going on around Q1 bugs me. If you're set on the Q1 part, you can fix it by mirroring the design top-to-bottom so the Q1 emitter is on the left, and can thus be a tiny jump to the VOUT connector. An alternative would be to seek out a transistor with a different pinout to achieve the same end.
Getting back to planes, you should split up your current single big plane. You don't want such a ready coupling path between the noisy AC and DC output sides, and probably want to segregate unreg and reg DC from each other, too. I would set up three grounds: UGND, CGND, and RGND. UGND is the unregulated ground, and connects all the grounds on the unregulated side of the board. CGND is the control ground; that is, for connections in the regulator proper. RGND is the regulated output ground, composed only of the GND pin on the VOUT connector and the output cap's ground. Each of these connects to its neighbor with a short, fat trace. Think of the separate planes as pools for current to swirl around in, not bothering the next pool down the line connected via a small stream.
As for how this maps to layers, I'm actually having trouble justifying a fourth layer, but you're going to get it for free... All you need is one more layer for the two or three segregated ground planes. You don't want to put them on different planes because you're trying to avoid creating a coupling path. Maybe you just create a mirrored pair of each plane, to lower the overall impedance.