The issue I would argue still lies in using the computer clock. In that thread they specify that the chip if the jitter input is low will correct for theoretically all of it, however if it is high it will still cause phase modulation.
I think the theoretical ideal would to be using error-correction transfer into a buffer and clock it out on the DAC side.
I actually contacted Bruno Putzeys a few years back. He didn't provide me with his detailled measurements for the SRC4192 but said that the jitter had to be at least in the "tens of ns" for the chip to revert to classical PLL operation. Gordon Rankin measured a PCM2706 at 3400ps (3.4ns).