

The problems is on the ES9018 , while it accpet the I2S, it had very rigorous request the I2S signal because its I2S input pots are without the master clock input.
I asked an engineer work for another manufacturer, he said in their gears , the I2S input will change to SPDIF then feed to the ES9018.
So I don't think the ES9018 can support I2S input as well.
But we have find the way to fix this problems.
The ES9018 must need the input master clock and built in a master clock selector can automatically choice between the I2S master clock and the 80MHz main clock.
What is the problem with the I2S exactly?
While interfacing a Musiland device to the Buffalo DAC, I experienced dropouts with I2S. The drop outs went away after increasing the DPLL bandwidth. One would think it is because of jitter. The funny thing is that with SPDIF input, you can use the lowest DPLL bandwidth setting with no drop outs whatsoever.
The same problem (drop outs in I2S and no drop outs in SPDIF) has been reported for the TI PCM2707-based TPA USB interface and also the Teralink USB interface. The only reported exception is the HiFace.
I have programmed the chip where I can select the bandwidth of the DPLL, so for me it is easy as I just turn a knob, but it can also be done automatically by detecting lock errors and backing out on the dpll bandwidth setting until no lock errors are experienced.
We also have the software for the ES9018 once we start test the ES9018. The software can doing anythings with the ES9018.
We have try to adjust the DPLL to max but only slight improve.
And we also resetting the Registers 11 address, from 0x85 change to 0x9D, but also slight improve and can't fully fix.
But if change the Registers 11 address, the ES9018 working a bit steady but sound quality slight degrade, maybe just my mentation.


















, the Sabre chip plot thickens.




