I am using PLL for clock recovery (see attachment).
PLL 565 CLOCK RECOVERY (bit sync.)
What are the design criterion s for R1,C1,R2, and C4 ?
R2 and C4 determines free-running frequency of PLL.
What would be the selection for c2, which determines capture range ?
Does there any restriction on VCC selection as it affects lock range ?
Here I am using XOR to ensure frequent data transitions. That is to avoid Consecutive
Identical Digit (CID).
I am using this circuit in wireless communication to recover clock from received data for
bit synchronization.
PLL 565 CLOCK RECOVERY (bit sync.)
What are the design criterion s for R1,C1,R2, and C4 ?
R2 and C4 determines free-running frequency of PLL.
What would be the selection for c2, which determines capture range ?
Does there any restriction on VCC selection as it affects lock range ?
Here I am using XOR to ensure frequent data transitions. That is to avoid Consecutive
Identical Digit (CID).
I am using this circuit in wireless communication to recover clock from received data for
bit synchronization.
