All SPDIF receivers need clock to recover the I2S signal either from external clock source or in-chip PLL-VCO clock source. For the V2.5 DAC (Valab), the Dir9001 used the in-chip PLL-VCO to decode a biphase input signal with a sampling frequency from 28 kHz to 108 kHz. For the wm8805, it uses the external clock and its internal PLL to decode the biphase input. The quality of clock source and the internal PLL loop therefore determine the recovered digital audio quality. ^-^
The pins 13 and 14 of Dir9001 are to select the clock source for system clock. For pins 13 and 14 to 3.3v mod, it is to set the system clock to 512fs. It may means the internal PLLed 512fs is better than the other frequency.
Teraguy, thank you for your recent descriptions and clarifications, especially since jkeny has been looking at Chameleon. You seem to know the fine details very well. It's made me very curious, if you're willing to say. Who are you, where are you, and what's your experience concerning Teradak, Chameleon, and the Valab DAC?