I've been playing with two toy's recently. The first is a digital PLL and the second is a high bandwidth ADC. In my travels, I came across this electronic design article, and I got to thinking about the phase shift introduced by the feedback of an amplifier.
With the DPLL I'm playing with, there's series of buffers and programmable muxes creating the phase shift between the output and the feedback. Even with a very short buffer path (i.e. as little phase shift as possible) the phase shift is substantial, at least in the simulations I'm running.
The input/buffer stage of an ADC is comparable to the gain stage of an amplifier in my opinion, however usually gain isn't added in a buffer. It's easier to deal with resolution issues in the ADC instead of the buffer. That aside, I was trying to get my ADC to operate in a highly linear fashion without using class A amplification.
With that in mind, reading the article, I suspect the characteristic equation the author developed for the system is naive (or is DC-only). There's no guarantee the transfer characteristics of each opamp are close enough that the phase shift between them in the case presented is correctly removed by the opamp action. That's to say, I suspect Verror1 is not really equal to Verror2. On an aside, I don't necessarily like the author ignoring that Verror1 and Verror2 are going to be dependent on the frequency of the input.
For my purposes, I'm just going to build his circuit for my buffer stage except replace the two opamp IC's with a 2-opamp IC. Per IC, I suspect that the assorted biases and subsequently the phase-shift is very nearly matched.
But then I got to thinking: more generally, maybe buffering the negative feedback after any voltage division/filtering and ensuring that the buffer was adequately matched to the gain circuitry would be useful in the gain stage of an amplifier (as above with a dual opamp or spending the time to match discrete components). I'd think it would correctly set the feedback voltage to remove any distortion caused by phase.
I don't know much about the intricacies of amplifier design, nor do I know if running the gain stage in class A removes these issues. Nor do I know whether or not I'm imagining these issues or finding problems where no problems exist.
I just thought I'd share. Let me know if I'm wrong; most of the folks I work with don't have an opinion on this and I'd really like to hear what other people think.
With the DPLL I'm playing with, there's series of buffers and programmable muxes creating the phase shift between the output and the feedback. Even with a very short buffer path (i.e. as little phase shift as possible) the phase shift is substantial, at least in the simulations I'm running.
The input/buffer stage of an ADC is comparable to the gain stage of an amplifier in my opinion, however usually gain isn't added in a buffer. It's easier to deal with resolution issues in the ADC instead of the buffer. That aside, I was trying to get my ADC to operate in a highly linear fashion without using class A amplification.
With that in mind, reading the article, I suspect the characteristic equation the author developed for the system is naive (or is DC-only). There's no guarantee the transfer characteristics of each opamp are close enough that the phase shift between them in the case presented is correctly removed by the opamp action. That's to say, I suspect Verror1 is not really equal to Verror2. On an aside, I don't necessarily like the author ignoring that Verror1 and Verror2 are going to be dependent on the frequency of the input.
For my purposes, I'm just going to build his circuit for my buffer stage except replace the two opamp IC's with a 2-opamp IC. Per IC, I suspect that the assorted biases and subsequently the phase-shift is very nearly matched.
But then I got to thinking: more generally, maybe buffering the negative feedback after any voltage division/filtering and ensuring that the buffer was adequately matched to the gain circuitry would be useful in the gain stage of an amplifier (as above with a dual opamp or spending the time to match discrete components). I'd think it would correctly set the feedback voltage to remove any distortion caused by phase.
I don't know much about the intricacies of amplifier design, nor do I know if running the gain stage in class A removes these issues. Nor do I know whether or not I'm imagining these issues or finding problems where no problems exist.
I just thought I'd share. Let me know if I'm wrong; most of the folks I work with don't have an opinion on this and I'd really like to hear what other people think.
