Hi Folks,
I thought I'd share my DAC PCB design with you. Got the PCBs today and have it working in hardware mode.
The design is as follows:
Inputs:
Burr Brown PCM2707 USB to SPDIF converter
2 x Optical SPDIF
1 x Coaxial SPDIF (although I made a mess of the PCB footprint for the RCA socket)
Outputs:
RCA
De-jittered Optical SPDIF
SPDIF transciever: Wolfson WM8805 (multiplexed version of WM8804)
DACs: Wolfson 8740/41 in dual differential mode
Output filters: Analog Devices AD797s
Control: Xilinx FPGA over I2C bus to WM8805.
I have the Verilog written for this but underestimated the size of FPGA required so need to get the board re-spun. At the moment the WM8805 is configured in hardware mode (I thought ahead here and provided that option), and receives data nicely from one of the optical inputs.
NO caps in signal path, plenty of sites for decoupling caps. Pictured below...

Let me know your thoughts, I'll do a run of these if anyone's interested?
Cheers...
I thought I'd share my DAC PCB design with you. Got the PCBs today and have it working in hardware mode.
The design is as follows:
Inputs:
Burr Brown PCM2707 USB to SPDIF converter
2 x Optical SPDIF
1 x Coaxial SPDIF (although I made a mess of the PCB footprint for the RCA socket)
Outputs:
RCA
De-jittered Optical SPDIF
SPDIF transciever: Wolfson WM8805 (multiplexed version of WM8804)
DACs: Wolfson 8740/41 in dual differential mode
Output filters: Analog Devices AD797s
Control: Xilinx FPGA over I2C bus to WM8805.
I have the Verilog written for this but underestimated the size of FPGA required so need to get the board re-spun. At the moment the WM8805 is configured in hardware mode (I thought ahead here and provided that option), and receives data nicely from one of the optical inputs.
NO caps in signal path, plenty of sites for decoupling caps. Pictured below...

Let me know your thoughts, I'll do a run of these if anyone's interested?
Cheers...

























