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TPA6120 headphone amp

post #1 of 19
Thread Starter 
Here's my noob attempt at a TPA6120 based headphone amplifier. Here's the schematic. It's similar to the THS6012 preamp schematic in this article by Rod Elliot, although somewhat simplified.

The pcb dimensions are 1.7" by 1.3". That might actually be too small of a board area for the TPA6120 to efficiently dissapate heat though. For the power supply, I'll probably end up getting two TREAD's and connecting them together in order to get the necessary dual supply.

I've read in various posts that there's less distortion when the TPA6120 is used in an inverting configuration, like in the peranders' QRV-07 amp, although I'm not really sure where that comes from as I have read through the TPA6120 and THS6012 datasheets and didn't see any different distortion figures given for the two inputs. The TI evaluation module uses non-inverting inputs, so I did the same.

edit: I forgot to mention that all the surface mount resistors and capacitors are the 1206 package for easier soldering. The two input buffers are standard pinout SOIC opamps.
post #2 of 19
*edit - I should read posts before posting*

I'm working out a power supply for something similar to the dtpakiller design at the moment. (as mentioned in another thread)

it wouldn't be THAT difficult to incorporate something in the design...

check out the max1771, max774, max775 and max1605 from maxim ( www.maxim-ic.com )

You could have one for the pos(say max1771), one for the neg(say max774), and use a capacitance multiplier after them to make a 250uF cap look like a 2500uF cap for the input. Or alternatively you could use a max1771 and a TLE2426 (which would be simpler)

If you choose this route, you'd want to have smoothing caps after the dc-dc converters (or alternatively the capacitance multiplier/cap).

This way you can have a portable amp running on a few AA batteries...

Beyond that you could have say 3 spots as well for an external supply like a pair of treads- so you had a choice.
post #3 of 19
I looks good but make sure you 100n goes to the groundplane on the "solder side", avoid hot releaf pads for the vias.

Since I had a buffer I wanted to test inverting mode but I'm pretty sure of that the distortion is pretty low even in non-inverting mode.

If you have the amp in inverting mode the input lies still and can not cause any common mode distortion phenomena and this is valid in most amps by nature but in real life there may be other distortion sources which are bigger.

The gain you have chosen is a bit high but this is easy fixed if it happend to be too much.

Please note that the TPA6120 has 10 uA bias current so you will get som offset if you feed it via 47 ohms. I got 10 mV offset in one channel and 2 mV in the other with gain of 2 and otimized resistor values.

Don't forget at least two screwholes for the pcb! How should it be mounted?

Good luck with the amp.
post #4 of 19
Thread Starter 
Quote:
I looks good but make sure you 100n goes to the groundplane on the "solder side", avoid hot releaf pads for the vias.
What's the advantage of having the bypass capacitors connect to ground through the bottom side versus the top?

Quote:
Please note that the TPA6120 has 10 uA bias current so you will get som offset if you feed it via 47 ohms. I got 10 mV offset in one channel and 2 mV in the other with gain of 2 and otimized resistor values.
What value would be the best to minimize offset voltage?

Quote:
Don't forget at least two screwholes for the pcb! How should it be mounted?
Ya, I just haven't added them yet.

Thanks for the suggestions.
post #5 of 19
Quote:
Originally Posted by tyre
What's the advantage of having the bypass capacitors connect to ground through the bottom side versus the top?
Make sure you have the best possible HF ground. I use both sides. Your component side has a rather many traces so it might be good to use the downside also.

You are using a 1300 V/us device so a good pcb is essential in order to achieve good results.

My pcb's look like this:
http://home5.swipnet.se/~w-50674/hif...v07pcbsold.jpg
http://home5.swipnet.se/~w-50674/hif...v07pcbcomp.jpg

Quote:
Originally Posted by tyre
What value would be the best to minimize offset voltage?
Each input must "see" the same DC resistance and in your case it is:
R5 = R6//R7 //= in parallel
post #6 of 19
are you ground filling the backside? - you really should, and add lots of top-bottom shorting vias to minimize inductance (besides just the pwr-pad)

backside components esp bypass caps can reduce loop area and inductance - I use 0805 bypass caps, this part is fast enough to consider broadside caps - 4 caps in a 1206 terminated on the "12" sides - interleave +/- bypass for the least inductance

I'm always amused to see how often "symmetry" leads people to "optimally bad" power distribution like yours

+/- supply traces should be placed as close togther as physically possible to reduce magnetic coupling to signal loops - particularly with class ab output stages where the half-wave currents appear in each power trace guaranteeing considerable distortion in the magnetically coupled signals; D Self discusses this in power amps

the paired supply traces should cross signal traces at 90 degrees to further minimize coupling - with 4-layer boards you can keep gnd plane between signal and pwr traces
post #7 of 19
Thread Starter 
Quote:
are you ground filling the backside?
Yes.

Quote:
you really should, and add lots of top-bottom shorting vias to minimize inductance (besides just the pwr-pad)
Ok. Should they be added at random spots or in specific areas?

Quote:
this part is fast enough to consider broadside caps - 4 caps in a 1206 terminated on the "12" sides - interleave +/- bypass for the least inductance
Hmm, I'm not sure what you are talking about there. Are you saying that I should add bypass caps between the +/- rails in addition to the caps going from the + and - rails to ground?

Quote:
I'm always amused to see how often "symmetry" leads people to "optimally bad" power distribution like yours
You're right, symmetry for the sake of aesthetics was one of my goals. Perhaps that's a bad idea though.

Quote:
+/- supply traces should be placed as close togther as physically possible to reduce magnetic coupling to signal loops - particularly with class ab output stages where the half-wave currents appear in each power trace guaranteeing considerable distortion in the magnetically coupled signals; D Self discusses this in power amps

the paired supply traces should cross signal traces at 90 degrees to further minimize coupling - with 4-layer boards you can keep gnd plane between signal and pwr traces
Woah. I think I might have gotten in over my head here. Maybe I should just buy the tpa6120 eval module from TI and forget it.

Well, here's a revised version with a few of your suggestions I tried to add in (pic1, pic2). I'll post the .brd file later if anyone wants to take a try at it.

I appreciate the help jcx and peranders.
post #8 of 19
jcx, you have some points but it's getting more important the higher frequencies involved and also the output power. The magnetic field from mA currents in this pcb isn't very big. TPA6120 doesn't reguire 4-layer pcb.

Tyre, you have done a pretty good job and there is difference between a good pcb layout and have done everything that's possible.

I should perhaps move the ground vias closer to the caps in order to reduce inductance (which will reduce the imdeance a bit at very high frequencies).

Don't forget to add screwholes which should not be plated if that is possible for you.

I avoid 90 deg corners in traces, check my layouts so you see what I mean. In critical applactions sharp corners are not good for EMC and besides it looks nicer with cut or round corners..
post #9 of 19
peranders is correct that if you can get hf layout correct for stability you'll have a hard time seeing other effects in this small a board - but if you want to squeeze out more of the potential performance don’t ignore good layout, the introduced errors are small but the tpa is really good so its hard not to degrade it’s potential

the next criticism: your new ps routing puts ps trace thru the window recommended to cut down on cap coupling in the tpa feedback - maybe/maybe not a problem but ps trace counts as gnd at hf

sticking with 2 layers I would consider moving ps conn/entry and electrolytics to the middle of the board between input amps and tpa and using a pair of twisted insulated jumpers on the backside (right down against the gnd plane) to get power up to the top of the tpa - if you're unwilling use jumpers it could be even better to rotate the tpa 180 so the ps pins are right next to the relocated ps entry/bypass - after dragging signal input conn and opamps to the lower edge of the board and with output conn ~ same position, this gives maximum separation from the ps conn/wires and the shortest board paths for power

while pcb jumpers feel like a defeat of your routing skills I think many 2 layer layouts could be significantly improved in electrical performance by their judicious use – even twisting the jumpers for pwr distribution is practical in diy projects that are hand assembled, hand assy also allows jumpers on both front and back so you can keep gnd plane between trace crossings where you need extreme signal isolation between traces that must cross

I would also increase your clearance on the gnd fill, fringing field capacitance across a long narrow gap can add up and the Cu squeezing between pins in the smt input amps make the board unsolderable without solder mask and may well push solder mask tolerance too far – I’ve wanted to put guard rings around smt op amp input pins before and always concluded pcb fab/soldermask tolerances didn’t allow it
post #10 of 19
Quote:
Originally Posted by jcx
I’ve wanted to put guard rings around smt op amp input pins before and always concluded pcb fab/soldermask tolerances didn’t allow it
Overkill, don't you think but cool. Guard rings are only useful in extremely high impedance situiations like pH-meters etc. The ring is for sucking up leakage current in the surface of the pcb in the high impedance node, normally the non-inverting input.

Anyway, about clearance to groundplane, I use 12 mil insulation, see pictures above.
post #11 of 19
I’m not recommending guard rings (yet), I’m critical of the apparently too small clearance of the gnd fill - look at pic2 showing gnd fill sneaking between pins - I'm betting this is impractically small spacing

I certainly would go multiloop (with lots of gain in the output amp) before thinking about guard rings for audio – dc leakage current isn't important but guard rings also serve as electrostatic shield and low Z E field termination for fr4's dielectric effects - get the equivalent low da functionality of teflon boards at near zero cost - someone has actually patented audio amplifier application of pcb guarding

I have designed pH sensor front ends – use a dual cmos op amp and pin 5, + input of amp “B” is “self guarded” by the low Z of the feedback driven negative input at only a few mV potential difference and the + input at pin 5 is far as any pin can get from the power pins – works with smt pkg without surface trace between the pins
post #12 of 19
Thread Starter 
Quote:
peranders is correct that if you can get hf layout correct for stability you'll have a hard time seeing other effects in this small a board - but if you want to squeeze out more of the potential performance don’t ignore good layout, the introduced errors are small but the tpa is really good so its hard not to degrade it’s potential
I'm definitely willing to optimize layout if it means better performance. But unfortunately, things like 4-layer boards would be too expensive, at least for me.

Quote:
sticking with 2 layers I would consider moving ps conn/entry and electrolytics to the middle of the board between input amps and tpa and using a pair of twisted insulated jumpers on the backside (right down against the gnd plane) to get power up to the top of the tpa
That's a pretty good idea. I guess I could just jumper the input opamps' power pins as well. I assume the jumpers would be soldered to the bottoms of the vias right?

Quote:
I would also increase your clearance on the gnd fill, fringing field capacitance across a long narrow gap can add up and the Cu squeezing between pins in the smt input amps make the board unsolderable without solder mask and may well push solder mask tolerance too far
Quote:
Anyway, about clearance to groundplane, I use 12 mil insulation, see pictures above.
Ok. I think I had clearance set to the default 8 mil, but I'll increase it.

Quote:
I’ve wanted to put guard rings around smt op amp input pins before and always concluded pcb fab/soldermask tolerances didn’t allow it
Would it be better just to leave the gnd plane unfilled underneath the input opamps altogether in a similar method to the tpa6120?


After trying several layout variations, this (pic1, pic2) is the only one I could come up with to minimize the distance of the ps traces to the tpa6120 without significant component rearrangement. It's not exactly elegant, but I tried to keep the ps traces parallel throughout. If it's not sufficient though, then I guess I'll go with the jumper method.
post #13 of 19
you’re doing great to get anything from my verbal sharphooting at your layout

the main threat on this latest layout is the tpa supply lead current’s magnetic coupling to the output trace/wiring/connector, I would move the headphone output wiring/connector in this last layout to the left vertical edge of the board, and squeeze the tpa power traces together in the middle. The right output trace has to cross the tpa pwr trace to get to the left side of the board but since it can cross at 90 degrees the coupling should be negligible

the input op amps probably operate nearly class a ( any coupling would be only a gain error, not a distortion like class b ps currents would induce ) and they draw very little dynamic current in any event so trace placement is less critical but I would still move the upper rightwards heading horizontal pwr pair upwards to near the pwr entry caps and away from the right side tpa signal traces, likewise the pwr trace pair on the lower edge should move away from the input connector, upwards between/under the unused end of the tpa and clear of the input gain R block looks pretty good to me

a couple of pairs of vias every now and again flanking the pwr pair route on either side bridges the slot put in the bottom layer gnd fill plane by the pwr trace clearance – the vias stitch the edges of the slot to the top layer gnd fill (yes this is nearly pointless at audio frequencies)

Some crudely approximated numbers:

~10-15 nH/in inductance for close space 20 mil conductors (sorta aprox from Ott)

its probably hard to get mutual inductance coupling factor k > 0.1 without trying

100 Krad/s ~= 16 KHz, top of audio band and easy # to use

multiply all the above and you get ~ 150 uV/A for incidental magnetic field coupling per inch to close spaced power distribution trace – (for signal stuff nearly on top of the pwr route to get k anywhere close to 0.1 )

if you drive 32 Ohm headphones you get ~ -106 dB (/in) pwr supply current induced V noise @ 16 KHz in loops that manage to have 10% coupling factor to the power supply trace current magnetic field

hopefully these measures are adequate to get > 20 dB more isolation from ps magnetic current induced V so as to not impair the tpa’s 120 dB distortion spec
post #14 of 19
Quote:
Originally Posted by tyre
Ok. I think I had clearance set to the default 8 mil, but I'll increase it.
A good in order not making it too hard on yourself is to have an insulation distance so it will end up with 15 mil ground between 63 mil IC pads.

100 mil grid, 63 mil pad = 37 mil "space" between an IC pin.

15 mil trace of ground => 11 mil left => 12 mil do I use.

If you have a too tight groundplane it's very likely that the soldermask won't cover the groundplane => not cool if you use wave soldering => shorting jumpers => extra work
post #15 of 19
Thread Starter 
Quote:
I would move the headphone output wiring/connector in this last layout to the left vertical edge of the board, and squeeze the tpa power traces together in the middle. The right output trace has to cross the tpa pwr trace to get to the left side of the board but since it can cross at 90 degrees the coupling should be negligible
How about I just elimate the R9's, as they aren't really needed anyways, which would give plenty of space in between to route the tpa6120's power traces. As long as R8 is at least 10 ohms, then R9 shouldn't be needed. pic1, pic2

(I'm still trying to retain some of the aesthetically pleasing symmetry thing. )

Quote:
a couple of pairs of vias every now and again flanking the pwr pair route on either side bridges the slot put in the bottom layer gnd fill plane by the pwr trace clearance
I dont think there's enough room on either side of the pair of traces to fit them in.


Sorry if my posts are getting repetitive. Thanks for your help guys.
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