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# My feeble attempt at a discrete I/V stage - Page 3

Quote:
 Originally Posted by Porksoda No reason. We focused more on the overall design, and not so much on the implementation. Caps across the cascoding LEDs would probably help with distortion at high frequencies, and putting a cap between the current mirror's bases and their respective power rails would probably help prevent oscillation. I recommend you take your queues from Malcolm's paper about where to add capacitors, and of course determine WHY the capacitor is there and what the impedences are in the surrounding circuit so you can choose values appropriately. I never did build this thing ("life" stepped in and has kept me busy since :-/ ) so I would be curious to hear how to do. 'soda
Thanks for the advice. I don't think I need the caps in the current mirror with the devices I'll be using, but I plan to put the pads in for that if it turns out to oscillate in practice.

I guess the main thing I am sweating before finalizing my drawing is base current cancellation. I don't think it can be ignored totally. For example, the current in T7 will tend to be about 98% of the current in T2 (assuming hfe = 400), which will contribute to the impedance seen by the DAC.

Then there's the problem that the current at T17's collector is +Idac - 7 * Ib, but the current at the collector of T18 is -Idac - 9 * Ib. The output will swing more on the low side than the high side, causing a substantial gain error of a whopping 4%. If I'm trying to realize a 140dB SNR, this is a major problem

So I think I need to put more thought into base current cancellation and/or making the circuit a bit more symmetric.

Quote:
 Originally Posted by jwb Thanks for the advice. I don't think I need the caps in the current mirror with the devices I'll be using, but I plan to put the pads in for that if it turns out to oscillate in practice. I guess the main thing I am sweating before finalizing my drawing is base current cancellation. I don't think it can be ignored totally. For example, the current in T7 will tend to be about 98% of the current in T2 (assuming hfe = 400), which will contribute to the impedance seen by the DAC. Then there's the problem that the current at T17's collector is +Idac - 7 * Ib, but the current at the collector of T18 is -Idac - 9 * Ib. The output will swing more on the low side than the high side, causing a substantial gain error of a whopping 4%. If I'm trying to realize a 140dB SNR, this is a major problem So I think I need to put more thought into base current cancellation and/or making the circuit a bit more symmetric.
I think you are being a little unrealistic with your expectations. There is a reason equipment that achieves the performance you are shooting for costs astronomical ammounts of money. Very very smart people went to school for a very very long time, and took a very very long time to design it. If you look inside a Wadia CD player you will see an output stage about eleventy billion times more complicated than what you are working with, and rightfully so. If you are that concerned about performance go buy a Wadia and save yourself years of agony.

With regards to current matching the inputs, consider this. For typical modeling, the resistance of the base to emitter connection is taken as 25 ohms. For a mismatch of 2% that is an effective resistance of 0.5 ohms. In a DAC that probably pushes no more than a couple milliamps, that is nothing. Furthermore, according to the ebers-moll equation (I think that is the name) collector current is actually exponentially related to Vbe, meaning that as you increase collector current this 0.5 ohm figure will decrease. At some point you have to accept that there is going to be a LITTLE impedence. Consider that some very respectable DACs accept input impedences in the 100s of ohms and somehow manage to get by just fine.

As far as output matching, you are correct about that mismatch, but you are talking about an effective mismatch of about 0.5% of the signal, and that is open loop! This circuit is designed to be used closed loop, so feedback will definitely bring that figure down. How much depends on how much feedback you use, which depends on how you choose to balance SNR and distortion.

Then again, there are PLENTY of other problems with this circuit if you want to split hairs, but I'll leave it to you to find them
Heh, I'm not afraid of Wadia (nor complexity), and I already spent all that time in school so I may as well try to take advantage of it

Thanks again for the further advice. I woke up this morning realizing that my analysis was flawed and there should not be a high/low drive mismatch at the output. So strike the last paragraph in my previous post.
What do you think of this alternative? It's non-Hawksford-related. The DAC current is applied to the emitters of Q3 and Q103. The input impedance should be around 4 Ohms and the simulator gives THD < 0.0005% at 1kHz.

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